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\begin{document}
\begin{center}
{\Large Operating Systems: Processes Study Guide}
\end{center}

\noindent\textbf{Three [4] Easy Pieces; Where We Are}
\begin{description}
\item[Persistence] Saving data across computer power cycles;
  \emph{non-volatile} memory can use magnetic or optical media or
  solid-state memory that remembers its state.
\item[\emph{Virtualization}] Emulating part (or all) hardware in
  system software to protect the actual hardware from direct access by
  running software. Can apply to the \emph{processor} and the
  \emph{memory}.
\item[Concurrency] Safely sharing resources across multiple processes
  that are running ``at the same time'', typically by ordering their
  instruction interleaving such that they behave as if they were run
  serially.
\item[Abstraction] Dr. Ladd's \emph{Fourth Easy Piece} The operating
  system provides a facade over heterogeneous hardware, an abstract
  interface that hides the complexity of the underlying systems.
\end{description}

\noindent \textbf{Mechanism} v. \textbf{Policy} --- Remember that
mechanism is \emph{how} the system can do something and policy is
deciding \emph{when} or \emph{why} to do it.

\vspace{3mm}
\hrule{}
\vspace{1mm}

\noindent \textbf{Hardware}
\vspace{-3mm}
\begin{multicols}{2}
\noindent
\textbf{Computer Hardware}
\begin{enumerate}
\item CPU
\item RAM
\item Disk(s)
\item I/O
\end{enumerate}

\noindent
\textbf{Memory Hierarchy}
\begin{enumerate}
\item Registers
\item RAM
\item Disks
\item Network
\end{enumerate}

\end{multicols}

\noindent \textbf{Von Neumann Architecture} --- CPU runs a
\emph{fetch-decode-execute}
cycle.\\
Program counter keeps track of next instruction.\\
Instructions can manipulate register contents \textbf{or} load
register from memory \textbf{or} store register to memory.\\
All data manipulation is at the CPU.

\noindent \textbf{Interrupts} The fetch-decode-execute cycle can be
interrupted \emph{asynchronously} by an \emph{interrupt signal}; the
\lstinline|syscall| instruction will also generate an interrupt when
run. Each interrupt has a number indicating its source (so the power
switch, \lstinline|syscall|, a timer expiring, and the network
controller signaling it is ready can be told apart) and that number is
used as an index into the \lstinline|ISV| \emph{interrupt service
  vector} (remember: vector = array), a vector of machine
\textbf{addresses} where the OS has put code to handle each kind of
interrupt.

\noindent
The \emph{k-stack} (kernel stack) is one way for the OS to capture the
context of the interrupted process. This \textbf{hardware assist} sees
the CPU copy full register contents onto the k-stack when the
interrupt is taken; the interrupt service routine can run and either
return from interrupt (back to the same process) \textbf{or} save the
contents of the k-stack, put the context of a different process there,
and return from interrupt into a different process.

\noindent \textbf{User/System Modes}\\
The \emph{privilege bit} is a CPU flag bit that determines whether the
CPU is currently executing on behalf of the \emph{system} or the
\emph{user}.

\noindent \textbf{Privileged Actions}
\begin{itemize}
\item Direct memory access (bypass memory address translation and page
  table).
\item Execution of CPU instructions deemed \emph{privileged}: setting
  CPU flags, installing interrupt handlers, I/O, etc.
\item Changing the CPU flags
\end{itemize}
The \emph{user} program runs with \textbf{limited-direct execution}:
non-privileged instructions run directly in a translated memory space
while privileged instructions require a \lstinline|syscall| (software
interrupt) into the operating system for the system to perform (after
checking that it is permitted) the operation.

\noindent \textbf{Speed/Safety Spectrum}

\begin{description}
\item[Unlimited Direct Execution:] \emph{Fast} execution with no
  protection of one process from another.
\item[Limited Direct Execution:] Compromise between speed and safety
\item[Virtual Execution:] \emph{Safe} execution with every instruction
  run in software.
\end{description}

\vspace{3mm}
\hrule{}
\vspace{1mm}
\noindent \textbf{Process Abstraction}

%\vspace{-6mm}
\begin{description}
\item[Program] Binary-encoded instructions in a \emph{file} on \emph{disk}.
\item[Process] Program file contents loaded into RAM along with \emph{context}
\end{description}

\noindent \textbf{Context} of a process is the setting of all CPU and
memory subsystem registers. The idea is that if the OS captures the
context of the running process, the CPU can do ``something else'' and
then, at some time in the future, put the saved context back and the
same process would continue running, unaware that it had been paused.

\noindent \textbf{Context Switch} is changing from the context
(execution) of Process A by \emph{saving} its context to the context
of Process B by \emph{loading} its context from a saved copy. This is
how two (or more) processes can share a single CPU concurrently.


\noindent \textbf{Process Data Structures} The OS keeps track of a
process in a \emph{process control block} (PCB); the PCB for all
processes as stored in an OS-level vector that is indexed by the
\emph{process identifier} (PID) of each process.

\noindent
In the PCB the OS keeps the \emph{context} of the process, memory
configuration, file control blocks, etc.

\noindent \emph{Process state} is one of the things tracked in the PCB
(the state is also indicated by where the PCB resides: Running, in a
ready queue, or in an I/O queue):

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  (3,3) node[minimum size=2cm,circle,fill=black!50!red,font=\sffamily] (blocked) {Blocked}
  (6,0) node[minimum size=2cm,circle,fill=black!50!green,font=\sffamily] (running) {Running};

\draw (running) edge[thick,bend right,-Stealth] node[above] {Descheduled} (ready);
\draw (ready) edge [thick,bend right,-Stealth] node[below] {Scheduled} (running);
\draw (blocked) edge [thick,bend left,-Stealth] node[below, sloped] {Complete I/O} (ready);
\draw (running) edge [thick,bend left,-Stealth] node[below, sloped] {Initiate I/O} (blocked);

\end{tikzpicture}
}

\noindent \textbf{Question:} What happens, at the CPU register level,
when a timer interrupt occurs, triggering a context switch between
process $S$ and process $T$? Include the \emph{k-stack}, the
\emph{privilege bit} and when it is set/cleared, and one or more
\emph{PCB} in your answer. What state(s) are $S$ and $T$ in
\emph{before} and \emph{after} the switch?

\noindent \textbf{Starting Processes}
\begin{description}
\item[\texttt{fork}] Copy the current process (with a new PID and
  PCB). Return PID of child (to parent) or 0 (to child).
\item[\texttt{exec}] Load the named file/program over the current
  process, resetting all registers and memory subsystem settings to
  process start values.
\end{description}

\vspace{3mm}
\hrule{}
\vspace{1mm}

\noindent \textbf{Scheduling}\\

\noindent \textbf{Scheduling Metrics} Which is important depends on
the type of \emph{workload} the system expects.
\begin{description}
\item[Turn-around Time] $T_{\textnormal{turn-around}} =
  T_{\textnormal{completion}}  - T_{\textnormal{arrival}}$; batch workloads
\item[Response Time] $T_{\textnormal{response}} =
  T_{\textnormal{firstrun}}  - T_{\textnormal{arrival}}$; interactive workloads
\end{description}

\noindent \textbf{Scheduling Policies}
\begin{description}
\item[First In, First Out]
\item[Shortest Job First]
\item[Shortest Time to Completion]
\item[Round Robin]
\end{description}

\noindent \textbf{Question:} Which of the given policies do not
require a mechanism for \emph{preemption}? Explain why the others do
require that mechanism.

\noindent \textbf{Multi-Level Feedback Queue} with a quantum length $q$.
Rules when picking the next job:
\begin{enumerate}
\item On arrival, job $J$ is put in $Q_{max}$.
\item If job $K$ surrenders the CPU before its quantum is done, it
  goes to the end of $Q_{P}$; its priority remains unchanged.
\item If job $K$ uses its whole quantum, it goes to the end of
  $Q_{P-1}$; its priority is lowered.
\item Next job to schedule is the first job on $Q_X$ where $X$ is the
  highest priority of a non-empty ready queue.
\item After the \emph{boost period}, $B$, $B \gg q$, all jobs are reenqueued into $Q_{max}$.
\end{enumerate}

\noindent \textbf{Question:} Why is rule 5 necessary? What if $\neg(B \gg q)$?

\noindent \textbf{Question:} Consider an MLFQ with: 3 queues, quantum of 1, allotment
  of 1, and a boost time of 25. The queues are numbered, in decreasing
  priority order: 3, 2, 1. Given the following list of jobs:

    \begin{tabular}{|r|r|r|}
    \hline
    Job&Arrival&Run Time\\\hline
    A&0&4\\\hline
    B&2&4\\\hline
    C&4&1\\\hline
    D&6&3\\\hline
  \end{tabular}

  Mark the quanta in which each job executes in the following table,
  using as the marker the \emph{number} of the queue the job was
  scheduled off of.

  So, for example, if Job D came off of queue 2 in the first quantum,
  there would be a ``2'' in row D and colunm 1 (the quantum starts at
  0, ends at 1).

  Before you mark anything:\\
  How many non-empty squares will there be in each row?\\
  How many in each column?\\
  How many total in the table?

  \begin{tabular}{|r|r|r|r|r|r|r|r|r|r|r|r|r|r|r|}
    \hline
    &\multicolumn{14}{c|}{Quantum Ending}\\\hline
    Job&1&2&3&4&5&6&7&8&9&10&11&12&13&14\\\hline
    A&&&&&&&&&&&&&&\\\hline
    B&&&&&&&&&&&&&&\\\hline
    C&&&&&&&&&&&&&&\\\hline
    D&&&&&&&&&&&&&&\\\hline
  \end{tabular}

  \begin{mdframed}


    How many columns? \textbf{12 (total quanta for all programs)}\\
    How many non-empty squares will there be in each row? \textbf{Run time of program in the row.}\\
    How many in each column? \textbf{One, there is only one CPU being scheduled.}\\
    How many total in the table? \textbf{12, one per column or one per
    quantum where a program is running.}


    \begin{tabular}{|r|r|r|r|r|r|r|r|r|r|r|r|r|}
      \hline
      &\multicolumn{12}{c|}{Quantum Ending}\\\hline
      Job&1&2&3&4&5&6&7&8&9&10&11&12\\\hline
      A  &3&2& & & &1& & & &1& & \\\hline
      B  & & &3&2& & & & &1& & &1\\\hline
      C  & & & & &3& & & & & & & \\\hline
      D  & & & & & & &3&2& & &1& \\\hline
    \end{tabular}
  \end{mdframed}


\end{document}

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